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TSMC Calls for New EDA Paradigm EE Times

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SAN FRANCISCO – Engineers need a new class of tools to keep up with the complexity of designing today's semiconductors, said a keynoter at the International Solid State Circuits Conference (ISSCC) here Monday (Feb. Separate tools need to target today's four major markets using new techniques and assumptions including machine learning, said Cliff Hou, vice president of R&D at TSMC. "We need a new design paradigm to overcome chip design challenges," said Hou. "It's time for us to evolve our design paradigm, we've only covered a small portion of" the design space, he said. Over the last 10 years the industry has been driven by mobile, building its design databases around smartphone SoCs. "Now we realize mobile is OK as a starting point but we also have to optimize circuits for automotive, high- performance systems and IoT where the considerations are very different," Hou said, showing four different SRAM designs TSMC uses just for a range of mobile and wearable designs. Hou's keynote gave a laundry list of knotty challenges where TSMC is seeing some progress.